Patent
1997-03-19
1999-03-23
Donaghue, Larry D.
395391, 395392, 395393, 395394, 395395, 395309, 395563, G06F 15163
Patent
active
058871853
ABSTRACT:
A microprocessor has an interface between a reorder buffer and a floating point unit, including a retire signal provided by the reorder buffer and a valid signal provided by the floating point unit. When the reorder buffer detects a floating point instruction which is ready to be retired, the reorder buffer pulses the retire signal. When the floating point unit executes the floating point instruction and produces a corresponding instruction result, the floating point unit pulses the valid signal. Upon assertion of both the retire signal and the valid signal, the floating point instruction is retired by the floating point unit. The reorder buffer retires the floating point instruction upon asserting the retire signal. Either the valid signal or the retire signal may be asserted first (in a temporal sense) for the floating point instruction. The receiving unit for the signal asserted first stores the signal in a shift register until the receiving unit detects the particular floating point instruction. The received signal pulse is then associated with the particular floating point instruction. Additionally, the interface may include a cancel signal provided by the reorder buffer in cases in which a floating point instruction is canceled, as well as an exception signal provided by the floating point unit instead of the valid signal if the particular floating point instruction experiences an exception. Finally, the interface may include a pair of signals for synchronizing the floating point unit and the reorder buffer upon detection of a floating point synchronization instruction.
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Donaghue Larry D.
Kivlin B. Noel
Pries Catherine
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