Dual damascene process for multi-level metallization and interco

Details Dual damascene process for multi-level metallization and interco Dual damascene process for multi-level metallization and interco

1998-02-13

1999-11-02

Niebling, John F.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438647, 438648, 438645, 438669, H01L 214763, H01L 2144

Patent

active

059769670

ABSTRACT:
The method of metallization includes the steps as follows. At first, a semiconductor substrate is provided and a dielectric layer is formed over the semiconductor substrate. A portion of the dielectric layer is removed to form contact holes and a first conductive layer is formed within the contact holes and over the dielectric layer. A portion of the first conductive layer is removed to define a contact pattern. Using the first conductive layer as a mask, a portion of the dielectric layer is removed to form openings within the dielectric layer and over the first conductive layer. A second conductive layer is then formed within the openings and over the first conductive layer. To planarize the surface of the semiconductor substrate, a portion of the second conductive layer and the first conductive layer is removed to planarize to the dielectric layer.

REFERENCES:
patent: 5354712 (1994-10-01), Ho et al.
patent: 5358901 (1994-10-01), Fiordalice et al.
patent: 5598027 (1997-01-01), Matsuura
patent: 5817572 (1998-10-01), Chiang et al.
patent: 5891799 (1999-04-01), Tsui
David Butler "Options for multilevel metallization" in Solid State Technology p. s7, Mar. 1996.
K. Kikuta et al. "Multilevel Planarized-Trench-Aluminum (PTA) Interconnection using Reflow Sputtering and Chemical Mechanical Polishing" (in IEDM Tech. Dig. p. 285, 1993).
R.V. Joshi "A New Damascene Structure for Submicrometer Interconnect Wiring" in IEEE Electron Device Letters, vol. 14, No. 3, 1993.

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