EEPROM having coplanar on-insulator FET and control gate

Details EEPROM having coplanar on-insulator FET and control gate EEPROM having coplanar on-insulator FET and control gate

1996-07-01

1999-03-23

Munson, Gene M.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257 57, 257 66, 257318, 257347, H01L 29788

Patent

active

058863761

ABSTRACT:
An electrically erasable programmable read-only memory CEEPROM) includes a field effect transistor and a control gate spaced apart on a first insulating layer, a second insulating layer formed over the field effect transistor and the control gate and a common floating gate on the second insulating layer over the channel of the field effect transistor and the control gate, the floating gate thus also forms the gate electrode of the field-effect transistor. The EEPROM devices may be interconnected in a memory array and a plurality of memory arrays may be stacked on upon another. The invention overcomes the problem of using a non-standard silicon-on-insulator (SOI) CMOS process to make EEPROM arrays with high areal density.

REFERENCES:
patent: 4453234 (1984-06-01), Uchida

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