SRAM having improved soft-error immunity

Details SRAM having improved soft-error immunity SRAM having improved soft-error immunity

1996-10-22

1999-03-23

Meier, Stephen D.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257369, 257903, H01L 27108, H01L 2976, H01L 2994, H01L 31119

Patent

active

058863753

ABSTRACT:
An SRAM cell having improved soft error immunity connects each of the storage nodes of the SRAM cell to an overlying electrode having a textured surface which is separated from a constant potential plate electrode by a dielectric layer. The textured surface of the overlying electrode may be created by forming hemispherical-grained silicon on its surface, or by forming a fin structure on its surface. The textured surface of the overlying electrode provides increased capacitance between the overlying electrode and the constant potential plate electrode, thereby increasing the capacitance of the storage node.

REFERENCES:
patent: 5480826 (1996-01-01), Sugahara et al.
patent: 5618747 (1997-04-01), Lou
patent: 5619055 (1997-04-01), Meguro et al.
patent: 5639685 (1997-06-01), Zahurak et al.
Ikeda, S. et al., A Stacked Split Word-Line (SSW) Cell for Low Voltage Operation, Large Capacity, High Speed SRAMs, IEDM, IEEE, 1993, pp. 809-812 .

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