Sense circuit for non-volatile memory device

Details Sense circuit for non-volatile memory device Sense circuit for non-volatile memory device

1993-08-25

1994-05-03

Heyman, John S.

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

365204, 307530, G11C 700

Patent

active

053094000

ABSTRACT:
A sense circuit for a non-volatile memory device includes a selecting circuit for selecting a predetermined cell transistor by selecting a predetermined bit line which is connected to the predetermined cell transistor, a feedback type bias circuit for maintaining a potential of a bus line to a constant level and including a first transistor which flows a current to the bus line, a detecting circuit for detecting whether or not a current flows through the predetermined cell transistor so as to read a data from the predetermined cell transistor and including a terminal for outputting the read data, and a current source including a second transistor for forcibly supplying a predetermined current to the first transistor, so that a gate-source voltage of the first transistor is greater than a threshold voltage of the first transistor.

REFERENCES:
patent: 4494219 (1985-01-01), Tanaka et al.
patent: 4535259 (1985-08-01), Smarandoiu et al.
patent: 4758748 (1988-07-01), Takeuchi
patent: 4896297 (1990-01-01), Miyatake et al.
patent: 4899070 (1990-02-01), Ou et al.
"A 35-ns 64K EEPROM", Richard D. Jolly et al, 8107 IEEE Journal of Solid-State Circuits, vol. 20, No. 5, Oct. 5, 1985, New York, U.S., pp. 971-978.
"A 1-Mbit CMOS EPROM with Enhanced Verification", Roberto Gastaldi et al, vol. 34, No. 5, Oct. 1988, New York, U.S., pp. 1150-1156.

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