Redundancy scheme for a dynamic RAM

Details Redundancy scheme for a dynamic RAM Redundancy scheme for a dynamic RAM

1980-10-06

1983-06-21

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Bad bit

371 8, G11C 1140

Patent

active

043897150

ABSTRACT:
A redundancy scheme is described for replacing defective main memory cells in a dynamic RAM with spare memory cells. The spare cells are arranged in groups of spare rows and spare columns of memory cells such that a plurality of groups of spare rows and columns of cells are substituted for defective main rows and columns of cells so as to repair relatively large defects which impair adjacent rows and columns of main memory cells. In the preferred embodiment, the RAM includes a plurality of address buffers, each of which receives an incoming row address bit and then an incoming column address bit for sequentially outputting row and column address data. Associated with each buffer is a store for a defective row address, a store for a defective column address, and a comparator. The stores retain defective memory cell addresses which the comparator sequentially compares against the address data sequentially output by the buffer. When the comparator senses a match, a control signal is generated to initiate substitution of spare memory cells for the defective main memory cells.

REFERENCES:
patent: 4047163 (1977-09-01), Choate et al.
patent: 4250570 (1981-02-01), Tsang et al.
patent: 4310901 (1982-01-01), Harding et al.

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