Phase locked loop and multi-stage phase comparator

Details Phase locked loop and multi-stage phase comparator Phase locked loop and multi-stage phase comparator

1997-12-23

2000-09-26

Chin, Stephen

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375371, 375373, 375374, 375375, 375327, 327156, 327158, 327159, 327236, 327244, 331 10, 331 11, 331 25, H03D 324, H04L 700, H04L 2500, H04L 2540

Patent

active

061251585

ABSTRACT:
The disclosure describes a multi-stage phase comparator and a phase-locked loop incorporating such a comparator. The comparator measures a phase difference between a reference signal and an output signal using a periodic clock. The comparator is a two stage comparator comprising a fine and coarse comparator. The coarse comparator measures the number of full clock periods between a transition of the reference signal and the output signal. The fine comparator comprises a delay line generator that generates a plurality of delayed clocks. The delayed clocks are used to over sample the reference signal to determine a fine phase difference representing a remaining fraction of the clock period, between transitions of the reference and output signals. A phase locked loop using the multi-stage comparator allows for more accurate phase locking.

REFERENCES:
patent: 4280104 (1981-07-01), Rzeszewski
patent: 4672447 (1987-06-01), Moring et al.
patent: 5486792 (1996-01-01), Girardeau, Jr.
patent: 5499274 (1996-03-01), Brown
patent: 5604775 (1997-02-01), Saitoh et al.
patent: 5691669 (1997-11-01), Tsai et al.
patent: 5870002 (1999-02-01), Ghaderi et al.
patent: 5875163 (1999-02-01), Kuroda et al.

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