Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1992-02-06
1994-04-12
Dixon, Joseph L.
Static information storage and retrieval
Read/write circuit
Bad bit
3642641, 3642685, 3649663, 36518901, 36523003, 36523004, 371 101, 371 102, 371 211, G11C 700, G06F 1116
Patent
active
053031920
ABSTRACT:
A semiconductor memory device storing data having a unit of N bits (N is an integer) includes M memory elements (M is an integer and larger than N) each divided into a plurality of blocks each having a plurality of memory cells each storing one-bit data, and M internal bus lines each carrying one-bit data and connected to a corresponding one of the M memory elements. A designating circuit receives an address signal from an external device and designates one of the plurality of blocks of each of the M memory elements so that M blocks are designated by the address signal. A ROM stores information on whether or not each of the plurality of blocks of each of the M memory elements has a defective memory cell and outputs the information in accordance with the address signal. N external bus lines individually carry one-bit data. A bus line switching circuit determines whether each of the M blocks designated by the designating circuit has a defective memory cell by referring to the information from the ROM, and selectively connects N internal bus lines among the M internal bus lines to the N external bus lines so that one of the M blocks which has a defective memory cell is prevented from being selected and another one of the M blocks is selected.
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Dixon Joseph L.
Fujitsu Limited
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