Input buffer providing virtual hysteresis

Details Input buffer providing virtual hysteresis Input buffer providing virtual hysteresis

1997-12-22

2000-09-26

Tokar, Michael

Electronic digital logic circuitry

Interface

Current driving

326 83, 326 87, 326 86, 326 31, 326 34, 326 33, 326 24, 327108, 327112, 327262, 327205, 327206, H03K 19003, H03K 190175, H03K 3037, H03B 100

Patent

active

061247332

ABSTRACT:
An input buffer includes a first CMOS inverter (400) made up of a PMOS transistor (602) connecting Vdd to the buffer output and an NMOS transistor (604) connecting the buffer output to Vss. NMOS transistors (404) and (414) have with series connected source to drain paths to connect the buffer output to Vss in conjunction with transistor (604) of inverter (400). PMOS transistors (402) and (412) have series connected source to drain paths connecting Vdd to the buffer output in conjunction with transistor (602). To control transistors (402, 404, 412 and 414) an inverter (420) is connected from the buffer output to the gates of transistors (402 and 404), and inverters (431, 432, 433, and 440) are connected between the buffer input and the gates of transistors (412 and 414). After a low to high buffer input transition above a level (H1), the inverter (420) will transition and the NMOS transistors (404 and 414) will turn on together to create a path to Vss with transistor (604) of inverter (400) to decrease the buffer threshold to (H2). After the buffer input rises further above a threshold (H1A) of inverter (431) combined with inverter (440), inverter (433) will turn off transistor (414) to set the buffer threshold back to (H1). After a high to low buffer input transition below a level (H1), the inverter (420) will transition and the PMOS transistors (402 and 412) will both be on together to create a path to Vdd with transistor (602) of inverter (400) to increase the buffer threshold to (H3). After the buffer input falls further below a threshold (H1B) of inverters (431) and (440), inverter (433) will turn off transistor (412) to set the buffer threshold back to (H1).

REFERENCES:
patent: 4506168 (1985-03-01), Uya
patent: 4539489 (1985-09-01), Vaughn
patent: 5023472 (1991-06-01), Hashimoto et al.
patent: 5198699 (1993-03-01), Hashimoto et al.
patent: 5349246 (1994-09-01), McClure
patent: 5459437 (1995-10-01), Campbell
patent: 5559461 (1996-09-01), Yamashina et al.
patent: 5594361 (1997-01-01), Campbell
patent: 5654981 (1997-08-01), Mahant-Shetti et al.
patent: 5668488 (1997-09-01), Sharpe-Geisler et al.
patent: 5676728 (1997-10-01), Cudos
patent: 5760620 (1998-06-01), Doluca

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