SRAM with flash clear for selectable I/OS

Details SRAM with flash clear for selectable I/OS SRAM with flash clear for selectable I/OS

1993-03-03

1993-11-30

Kriess, Kevin A.

Static information storage and retrieval

Read/write circuit

Erase

307465, G11C 1140

Patent

active

052672107

ABSTRACT:
A static random access memory having multiple I/Os includes a memory array (10) of memory cells (42) with columns that are selectively clearable as a function of the associated I/O. The columns are arranged in pairs (34) with each column in the pair (34) associated with the same I/O. A clear signal is input thereto on a line (28) and driven by a driver (30). The clear signal is only associated with the pairs (34) associated with a selected I/O. The remaining columns of memory cells associated with unselected I/Os are not cleared.

REFERENCES:
patent: 4408306 (1983-10-01), Kuo
patent: 4442510 (1984-04-01), Priel et al.
patent: 4567578 (1986-01-01), Cohen et al.
patent: 4587629 (1986-05-01), Dill et al.
patent: 4680734 (1987-07-01), Baba et al.
patent: 4758990 (1988-07-01), Uchida
patent: 4879686 (1989-11-01), Suzuki et al.
patent: 4881206 (1989-11-01), Kadono
patent: 4882708 (1989-11-01), Hayakawa et al.

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