Read/write memory having an improved write driver

Details Read/write memory having an improved write driver Read/write memory having an improved write driver

1990-12-13

1993-11-30

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

365190, 365207, 365208, G11C 700

Patent

active

052671976

ABSTRACT:
A static random-access memory is disclosed which utilizes bit line pairs for each column of memory cells for communication of data between external data terminals and the memory cells. A precharge transistor is connected between each bit line and a precharge voltage, for example V.sub.cc, and an equilibration transistor is connected between the bit lines in each bit line pair. The precharge and equilibration transistors are controlled according to selection of the column, so that all columns which are not selected by the column address are precharged and equilibrated, including the unselected columns in the same sub-array as the selected columns. In an additional embodiment of the invention, a data transition detection circuit also controls the precharge and equilibration transistors, so that the precharge and equilibration transistors for the selected columns are turned on responsive to an input data transition during a write operation; this assists the write drivers in more quickly writing the new data onto the bit lines. Source followers are provided in the write drivers, connected to the input/output lines, to assist in the write recovery (i.e., in pulling the input/output lines high upon completion of the write operation), without requiring critical timing control. The source followers also serve to clamp the bit line voltage swing during a read, without providing a load on the bit lines during establishment of the differential voltage thereupon.

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Tran, et al., "An 8ns BiCMOS 1Mb ECL SRAM with a Configurable Memory Array Size", Digest of Technical Papers, 1989 IEEE International Solid-State Circuits Conference (IEEE, 1989), pp. 36-37.

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