Transistor layout for semiconductor integrated circuit

Details Transistor layout for semiconductor integrated circuit Transistor layout for semiconductor integrated circuit

1994-07-01

1996-03-12

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257369, 257927, H01L 2711, H01L 29772

Patent

active

054988977

ABSTRACT:
A semiconductor integrated circuit comprising a MOSFET having a metal wiring layer formed via an insulating film above and along the gate electrode of the MOSFET. The MOSFET is structured such that its channel length is small or channel width is large, and an input signal is applied from at least both end sides of the gate electrode thereof. Since the metal wiring layer for the input signal is formed on the gate electrode of the MOSFET, high-speed operation is possible without increasing the layout area. FIG. 1.

REFERENCES:
patent: 4673969 (1987-06-01), Ariizumi
patent: 5027185 (1991-06-01), Liauh
Leung et al, IEEE-IEDM Tech Dig. 1980 pp. 827-830 Wash D.C. "Refractory in CMOS/SOS".

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