Semiconductor memory cell having high density structure

Details Semiconductor memory cell having high density structure Semiconductor memory cell having high density structure

1992-03-26

1992-12-15

Jackson, Jr., Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257758, H01L 2978, H01L 2350

Patent

active

051722020

ABSTRACT:
In a semiconductor memory cell of a DRAM comprising a stacked cell capacitor constructed upon word and bit lines, the stacked cell capacitor is not directly connected to a transistor to the device isolator area is provided. Through this wiring, the diffusion layer of the transistor is connected to the stacked cell capacitor. Also, a bit line is constructed on the active region to cross the connection point between the transistor, local wiring and gate electrode.

REFERENCES:
patent: 4970564 (1990-11-01), Kimura et al.
Kimura et al. IEDM 1988, pp. 596-599 "A New Stacked Capacitor DRAM . . . Structure".
T. Ema et al, "3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMs", IEDM Technical Digest, pp. 592-595 (1988).

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