MOS type semiconductor device

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Patent

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Details

365184, 365185, 257390, 257648, H01L 2968, G11C 1700

Patent

active

051721988

ABSTRACT:
A MOS type semiconductor device includes two adjacent MOSFETs. The FETs are respectively formed on element forming areas of a P-type substrate. Each of the transistors has N.sup.+ type layers serving as the source and drain thereof and they have a common gate electrode layer. Each of the FETs has a contact hole formed in one of the N.sup.+ type layers. A wiring layer is to be connected to the contact hole. A P.sup.+ type heavily doped semiconductor layer substantially intersects the common gate electrode layer between the FETs in the substrate. The layer functions as an inversion prevention layer. The inversion prevention layer projects from the common gate electrode layer towards the contact hole. The common gate electrode layer has a concave portion in an area of intersection with the inversion prevention layer, whereby an effective projection distance of the inversion prevention layer is increased while an opposition distance between the front edge of the inversion prevention layer and the contact hole section is kept from being set to be less than a previously required value.

REFERENCES:
patent: 4451904 (1984-05-01), Sugiura et al.
patent: 4477883 (1984-10-01), Wada
patent: 4783766 (1988-11-01), Samachisa et al.
patent: 4903086 (1990-02-01), Hackley
patent: 5031011 (1991-07-01), Aritome et al.

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