Semiconductor memory device with precharge time improved

Details Semiconductor memory device with precharge time improved Semiconductor memory device with precharge time improved

1997-02-04

1997-12-30

Le, Vu A.

Static information storage and retrieval

Read/write circuit

Accelerating charge or discharge

365203, 3652335, 365210, 3651852, 36518525, G11C 700

Patent

active

057038201

ABSTRACT:
A semiconductor memory device includes a memory cell array composed of a plurality of memory cells arranged in a matrix manner and at least one reference memory cell, wherein a plurality of digit lines are respectively connected to columns of memory cells, a plurality of word lines are respectively connected to rows of memory cells, and a reference digit line is connected to the reference memory cell, an address circuit for selecting one of the plurality of digit lines and one of the plurality of word lines in response to input of an address to select one of the plurality of memory cells, a sense amplifier connected to the plurality of digit lines and the reference digit line, for sensing data which has been stored in the selected memory cell in response to a first portion of a sense control signal, a discharging circuit for discharging charge of at least one of the plurality of digit lines which is connected to the selected memory cell and charge of the reference digit line in response to a second portion of the sense control signal, and a control section for outputting the sense control signal to the sense amplifier and the discharging circuit in response to the input of the address.

REFERENCES:
patent: 4713797 (1987-12-01), Morton et al.
patent: 4872143 (1989-10-01), Sumi
patent: 4922461 (1990-05-01), Hayakawa et al.
patent: 5313434 (1994-05-01), Abe

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