Sputter and CVD deposited titanium nitride barrier layer between

Details Sputter and CVD deposited titanium nitride barrier layer between Sputter and CVD deposited titanium nitride barrier layer between

1996-03-07

1998-02-10

Thomas, Tom

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257760, 257764, 257769, 257770, H01L 2348, H01L 2352

Patent

active

057172501

ABSTRACT:
This invention is a process for forming an effective titanium nitride barrier layer between the upper surface of a polysilicon plug formed in thick dielectric layer and a platinum lower capacitor plate in a dynamic random access memory which is being fabricated on a silicon wafer. The barrier layer process begins by etching the upper surface of the polysilicon plug using a selective polysilicon etch until it is recessed at least 1000 .ANG. below the upper surface of the thick dielectric layer. Using a collimated sputter source, a titanium layer having a thickness of 100-500 .ANG. is deposited over the surface of the in-process wafer, thus covering the upper surfaces of the polysilicon plugs. A layer of amorphous titanium carbonitride having a thickness of 100-300 .ANG. is then deposited via low-pressure chemical vapor deposition. This is followed by the deposition of a reactively sputtered titanium nitride layer having a thickness of 1000-2000 .ANG.. The wafer is then planarized to remove the titanium, titanium carbonitride and titanium nitride, except that which is in the recesses on top of the silicon plugs. The wafer is then annealed in nitrogen to react the titanium layer with the silicon on the upper surfaces of the plugs to form titanium silicide. A platinum layer is then deposited and patterned to form lower capacitor electrodes which are electrically coupled to the polysilicon plugs through the titanium silicide, titanium nitride and titanium carbonitride layers.

REFERENCES:
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patent: 5136362 (1992-08-01), Grief
patent: 5246881 (1993-09-01), Sandhu
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patent: 5381302 (1995-01-01), Sandhu et al.
IBM Technical Disclosure Bulletin, vol. 35, No. 5, Oct. 1992 (Collimated Sputtering).

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