Set associative cache memory system with reduced power consumpti

Details Set associative cache memory system with reduced power consumpti Set associative cache memory system with reduced power consumpti

1998-11-06

2000-06-13

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

711128, 713324, G06F 1206

Patent

active

060761407

ABSTRACT:
A memory design which facilitates incremental and store requests off an applied base address request increases the bandwidth of cache via the use of an internal address generation facility built into the memory's decoding circuitry. The introduction of an internal address generation facility simplifies extraneous control of typical requesters built into a memory system. The memory design also reduces power consumed by requests which exploit the memory's internal address generation facility. Power consumption is further reduced in a set associative cache memory system by enabling one set of sense amplifiers during an incremental fetch.

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patent: 5691956 (1997-11-01), Chang et al.
patent: 5715426 (1998-02-01), Takahashi et al.
patent: 5778428 (1998-07-01), Batson et al.
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patent: 5784712 (1998-07-01), Byers et al.
patent: 5848428 (1998-12-01), Collins
patent: 5918044 (1999-06-01), Levitan et al.

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