Semiconductor static random access memory device with low power

Static information storage and retrieval – Systems using particular element – Flip-flop

Patent

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Details

Other Related Categories

365190, 365203, G11C 1100

Type

Patent

Status

active

Patent number

061478989

Description

ABSTRACT:
There is disclosed an SRAM including a number of memory cells located in the form of a matrix. When data "0" is written to a memory cell 100, a precharge signal PC is brought to a high level so that a bit line D0 is brought into an electrically floating condition. A corresponding power switch 30 is turned off so that a pseudo-ground line SS0 is brought to an electrically floating condition. A corresponding equalizing transistor 20L is turned on so that the bit line having a power supply voltage Vdd as an initial potential and the pseudo-ground line SS0 having a ground voltage Vss as an initial potential are electrically connected to each other, so that the potential of the pseudo-ground line SS0 is elevated to a potential Veq which is determined by a ratio in capacitance of the bit line and the pseudo-ground line. As a result, the data holding capability of the memory cell 100 is lowered, and therefore, when a corresponding word line is pulled up, a latch in the memory cell 100 is quickly inverted, so that the writing operation is completed at a high speed. After the writing operation, the potential of the bit line D0 is returned to the initial potential Vdd. In this operation, since the potential of the bit line D0 was lowered only to the potential Veq, the potential of the bit line D0 is returned to the initial potential Vdd quickly with a reduced power consumption.

REFERENCES:
patent: 4780847 (1988-10-01), Ito
patent: 5491661 (1996-02-01), Motomura
patent: 5523966 (1996-06-01), Idei et al.
patent: 5771190 (1998-06-01), Okamura

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