Semiconductor devices having gate stack with improved sidewall i

Details Semiconductor devices having gate stack with improved sidewall i Semiconductor devices having gate stack with improved sidewall i

1999-05-28

2000-06-13

Hardy, David

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257900, 257915, 438595, 438653, H01L 2978

Patent

active

060752742

ABSTRACT:
A process of manufacturing a gate stack whereby the integrity of both the gate sidewalls and the substrate surface is maintained. Nitride spacers are constructed on the sidewalls of a gate which has been etched only to the top of the polysilicon layer. This allows more of the polysilicon sidewall to be exposed during subsequent reoxidation while at the same time minimizing effects such as bird's beak resulting during reoxidation. After the nitride spacers are constructed the subsequent etch is performed in two steps in order to minimize degradation of the substrate surface in underlying active regions.

REFERENCES:
patent: 5032530 (1991-07-01), Lowrey et al.
patent: 5087584 (1992-02-01), Wada et al.
patent: 5103272 (1992-04-01), Nishiyama
patent: 5146291 (1992-09-01), Watabe et al.
patent: 5175606 (1992-12-01), Tsai et al.
patent: 5235204 (1993-08-01), Tsai
patent: 5268330 (1993-12-01), Givens et al.
patent: 5272367 (1993-12-01), Dennison et al.
patent: 5382551 (1995-01-01), Thakur et al.
patent: 5422291 (1995-06-01), Clementi et al.
patent: 5425392 (1995-06-01), Thakur et al.
patent: 5438016 (1995-08-01), Figura et al.
patent: 5439838 (1995-08-01), Yang
patent: 5459345 (1995-10-01), Okudaira et al.
patent: 5468665 (1995-11-01), Lee et al.
patent: 5538906 (1996-07-01), Aoki
patent: 5545578 (1996-08-01), Park et al.
patent: 5583368 (1996-12-01), Kenney
patent: 5597756 (1997-01-01), Fazan et al.
patent: 5608249 (1997-03-01), Gonzalez
patent: 5624865 (1997-04-01), Schuegraf et al.
patent: 5668394 (1997-09-01), Lur et al.
patent: 5681768 (1997-10-01), Smayling et al.
patent: 5739066 (1998-04-01), Pan
Beyers, R., "Thermodynamic Considerations in Refractory Metal Silicon-Oxygen Systems", J. Appl. Phys., 56, 147-152, (Jul. 1984).
Kasai, K., et al., "W/WNx/Poly-Si Gate Technology for Future High Speed Deep Submicron CMOS LSIs", IEDM 1994, 497-500, (1994).
Lee, D.H., et al., "Gate Oxide Integrity (GOI) of MOS transitors with W/TiN stacked gate", 1996 Symposium on VLSI Technology Digest of Technical Papers, 208-209, (1996).
Wolf, S., "Silicon Processing for the VLSI Era", vol. 3: The Submicron Mosfet, Lattice Press, 596, (1995).

Affiliated with

Also associated with

Rating

Semiconductor devices having gate stack with improved sidewall i does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor devices having gate stack with improved sidewall i, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor devices having gate stack with improved sidewall i will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2070599