Manufacturing capping layer for the fabrication of cobalt salici

Details Manufacturing capping layer for the fabrication of cobalt salici Manufacturing capping layer for the fabrication of cobalt salici

1998-12-08

1999-10-19

Quach, T. N.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

438655, 438664, 438683, 438902, H01L 2128

Patent

active

059703709

ABSTRACT:
An improved process for manufacturing cobalt silicide layers uses two capping layers. A first capping layer of titanium nitride prevents the formation of a cobalt/titanium intermetallic. A subsequently formed titanium metallic layer getters impurities from outgassing and the ambient preventing corruption of the cobalt layer. Two rapid thermal annealing steps convert the cobalt at the cobalt/silicon intermetallic into highly conductive cobalt disilicide. The cobalt silicide does not suffer from linewidth dependent increases in resistivity. Therefore, the cobalt disilicide formed by the present method is useful for semiconductor devices with linewidths and feature sizes less than 0.20 .mu.m. The process has wide applicability and may be used to fabricate local circuit interconnects, floating gates, double polysilicon stacked floating gates as well as other uses.

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