Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Patent
1998-02-26
2000-06-13
Chaudhari, Chandra
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
438446, 438622, 438643, 438644, H01L 218247
Patent
active
060749393
ABSTRACT:
It is an object of the invention to improve reliability of wiring layers in a semiconductor device comprising an intermetal insulator layer composed of a polysilazane SOG layer. A method for fabricating semiconductor device comprises the steps of forming a wiring layer provided with a oxidization-resisting metallic layer covering its outer surface on an underlying insulator layer, which is formed on a semiconductor substrate, forming a side wall insulator layer with penetration-resisting property against oxidizing gas around a wiring layer and the oxidization-resisting metallic layer, applying spin-on glass (SOG)-producing materiel composed of silicon compound materiel, which comprises silazane bonding in its back bone, thereon, and sintering the SOG-producing material in oxidization gas atmosphere.
REFERENCES:
patent: 5605867 (1997-02-01), Sato et al.
Wolf, Silicon Processing for the VLSI Era, vol. II, p. 232, 1990.
Chaudhari Chandra
Kilday Lisa
NEC Corporation
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