Isolated multi-chip devices

Details Isolated multi-chip devices Isolated multi-chip devices

1997-08-06

2000-11-14

Clark, Sheila V.

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including high voltage or high power devices isolated from...

257500, 257777, 257723, H01L 2900

Patent

active

061473936

ABSTRACT:
A semiconductor device structure in which a power semiconductor device is used as the substrate for the structure. Initially, a first metallization layer is formed on the power semiconductor device. Then, a dielectric passivation layer is formed over the first metallization layer, the dielectric passivation layer having apertures through which the first metallization layer may be accessed. A polymer passivation layer is then formed on the dielectric passivation layer, the polymer passivation layer also having apertures through which the first metallization layer and the dielectric passivation layer may be accessed. A second metallization layer is then formed on the polymer passivation layer and at least one electronic component is attached to the polymer passivation layer or the second metallization layer. The polymer passivation layer provides galvanic isolation between the power semiconductor device and the electronic component.

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