Method and device for address decoding in an integrated circuit

Details Method and device for address decoding in an integrated circuit Method and device for address decoding in an integrated circuit

1995-09-11

1998-04-21

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Signals

365195, 365196, 3652335, 36532006, G11C 700

Patent

active

057425469

ABSTRACT:
In a method for the decoding of the addresses of a memory, a pulse is generated at output of a filtering circuit at each change of address detected at the address bus to inhibit the address decoder during a determined duration. The filtering signal is applied more particularly to the row decoder which selects a row corresponding to an address applied to the input of the decoder and applies a control voltage to this row. This method is particularly advantageous in low-voltage memories.

REFERENCES:
patent: 5029135 (1991-07-01), Okubo
patent: 5400279 (1995-03-01), Momodomi et al.
patent: 5414659 (1995-05-01), Ito
patent: 5430682 (1995-07-01), Ishikawa et al.
Patent Abstracts of Japan, vol. 2, No. 149 (E-78), Dec. 13, 1978, and JP-A-53 117342 (Nippon Denki), Oct. 13, 1978.

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