Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1998-05-26
1999-10-19
Le, Vu A.
Static information storage and retrieval
Read/write circuit
Bad bit
36523003, 3652257, G11C 700
Patent
active
059700033
ABSTRACT:
A semiconductor memory device comprising at least one memory mat comprised of a plurality of memory cells respectively provided at points where a plurality of word lines and spare word lines respectively intersect a plurality of bit lines and spare bit lines placed so as to intersect the word lines and spare word lines. In the semiconductor memory device, a plurality of fuse means allowed to open or remain unopen in accordance with stored information encoded with respect to addresses for specifying defective word lines or defective bit lines are used to control gate means based on their corresponding complementary signals. Thus, the gate means transmit signals for selecting their corresponding word lines or bit lines to thereby produce coincidence
on-coincidence signals.
REFERENCES:
patent: 5532966 (1996-07-01), Poteet et al.
patent: 5652725 (1997-07-01), Suma et al.
patent: 5691952 (1997-11-01), Sasaki et al.
Kubouchi Shuuichi
Miyatake Shin-ichi
Hitachi , Ltd.
Hitachi ULSI Systems Co. Ltd.
Le Vu A.
LandOfFree
Semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2064858