Method and apparatus for programmable control signal generation

Details Method and apparatus for programmable control signal generation Method and apparatus for programmable control signal generation

1999-09-02

2000-10-31

Nelms, David

Static information storage and retrieval

Read/write circuit

Testing

365194, 365200, 326 39, 326 41, G11C 700

Patent

active

061412724

ABSTRACT:
A method and apparatus for testing of semiconductor memory devices. In one embodiment, a test mode of operation is defined for a memory device. In a normal mode of operation, a row line to an addressed memory cell is asserted in response to applied external signals corresponding to the beginning of a write-back phase of a read-modify-write cycle. The row line is deasserted on response to applied external signals corresponding to the end of the write-back phase. In the test mode of operation, the row line is asserted in response to the appropriate applied external signals, but deassertion in response to the appropriate applied external signals is suppressed. Instead, deassertion of the row line is forced only upon expiration of a programmable, predetermined time interval following initiation of the write-back phase. The programmable delay can be established by means of an R-C time constant delay circuit. Programmability may be achieved in various ways, including through the provision of metal options selected during the fabrication process, or, alternatively through the provision of laser-actuable fuses or voltage-actuable antifuses. The programmable forced write-back time facilitates reliable comparative testing of multiple parts, and compensates for part-to-part process variations which potentially impact operational performance of different parts to different degrees.

REFERENCES:
patent: 4905192 (1990-02-01), Nogami et al.
patent: 5506811 (1996-04-01), McLaury
patent: 5596538 (1997-01-01), Joo

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