Flash memory having separate data programming and erasing termin

Details Flash memory having separate data programming and erasing termin Flash memory having separate data programming and erasing termin

1996-07-26

1999-10-19

Chaudhuri, Olik

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257321, 257623, 438212, 438264, 438268, H01L 29788, H01L 2906

Patent

active

059693843

ABSTRACT:
A method of fabricating a flash memory having a vertical floating gate terminal layer and controlling gate terminal layer structure, which is suitable for use in ultra-high density IC circuits, and which has two separate tunneling layers, one used for data programming and the other used for data erasure. The fabrication method includes a number of steps. A protruding plateau is first formed on the surface of a silicon substrate. Then, ions are implanted to form a drain region on the top surface of the protruding plateau, as well as to form source regions in the substrate on each side of and adjacent to the base of the protruding plateau. A gate oxide layer is formed on each side wall of the protruding plateau; exposing only part of the side wall of the drain region. A tunnel oxide layer that is thinner than the gate oxide layer, is formed above the surface of the silicon substrate so as to cover the source regions and drain region. A floating gate terminal layer is formed on each side wall of the gate oxide layer and the drain tunneling oxide layer. A dielectric layer is then deposited over the substrate, and a controlling gate terminal layer is formed on each side wall of the dielectric layer.

REFERENCES:
patent: 5414287 (1995-05-01), Hong
patent: 5508544 (1996-04-01), Shah
patent: 5633519 (1997-05-01), Yamazaki et al.

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