Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1996-05-23
1998-04-21
Everhart, Caridad
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438666, 438672, 438700, H01L 2144
Patent
active
057417415
ABSTRACT:
A method for making planar metal interconnections and T-shaped metal plugs for integrated circuits is achieved. The method involves forming a planar insulating (SiO.sub.2) and a hard mask film over a first level of interconnections. A patterned first photoresist layer is then formed for etching trenches in the hard mask film and partially into the planar insulating layer (SiO.sub.2) in which a second level of interconnections are to be formed. The patterned photoresist layer is then laterally etched to expose the hard mask adjacent to the trenches in the SiO.sub.2, and the hard mask is then removed adjacent to the trenches to form a self-aligned mask for the metal plug contact openings. A patterned second photoresist mask aligned over the trenches is then used to etch the contact openings in the trenches, using the hard mask to form T-shaped plug contact openings to the first level of interconnections. The trenches and plug contact openings are concurrently filled with CVD aluminum and chem/mech polished back to form the second level of interconnections with T-shaped metal plugs. The T-shaped metal plugs improve the edge coverage while making it easier to fill the narrow contact openings with aluminum without voids in the metal plugs.
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K. Ueno, "A Half-Micron Pitch Cu Interconnection Technology" IEEE 1995 Symposium on VLSI Technology Digest of Technical Papers, pp. 27-28.
Ackerman Stephen B.
Everhart Caridad
Saile George O.
Vanguard International Semiconductor Corporation
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