Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Patent
1996-07-15
1998-04-21
Tsai, Jey
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
438406, 438401, 438459, H01L 2184, H01L 2100
Patent
active
057417334
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
In planar technology, which is chiefly used nowadays for semiconductor circuits, the integration level that can be achieved on a chip is limited by the size of the chip, on the one hand, and by the structural fineness that can be achieved, on the other hand. The performance of a system which is realized using planar technology and which comprises a plurality of chips connected to one another is limited by the number of possible connections between individual chips via connection contacts, the signal transmission speed that can be achieved via such connections (the so-called frequency performance), and also by the power consumption.
2. Description of the Related Art
The use of three-dimensional circuit arrangements has been proposed (see, for example, the publication by T. Kunio et al., IEDM '89, p. 837 or K. Oyama et al., IEDM '90, p.59) in order to overcome these restrictions. A plurality of chip planes are arranged one above the other in the three-dimensional circuit arrangements. The necessary electrical connections between the chip planes are produced by making direct contact.
In order to produce three-dimensional integrated circuits, it is known (see, for example, the publication by T. Kunio et al., IEDM '89, p. 837 or K. Oyama et al., IEDM '90, p.59) to deposit a further semiconductor layer on a substrate in which a plane of components has been produced. This semiconductor layer is recrystallized by laser annealing, for example. A further component plane is then realized in the recrystallized layer. The components produced in the substrate prior to the deposition of the further semiconductor layer are exposed, during the recrystallization step to the thermal loading associated with the laser annealing, which leads to a very limited yield for the chips due to large numbers of defects which occur.
In order to produce a three-dimensional integrated circuit arrangement, it is known, from the publication by Y. Hayashi et al. Syrup. VLSI Technol. 1990, p. 95, first to produce the individual component planes separately from one another in different substrates. These substrates are then thinned to a few .mu.m in thickness and are connected to one another with the aid of the wafer bonding method. For the electrical connection of the various component planes, the thinned substrates are provided on their front and rear sides with contacts for subsequent interchip connections. This has the disadvantage that the thinned wafers have to be processed on both the front and rear sides. However, rear side processes are not provided in the standard planar technology. A number of handling problems remain unsolved in connection with this method. A further disadvantage of the known method is that the functionality of the individual component planes cannot easily be tested before they are joined together, since individual components, but not complete circuits, are realized in each individual plane.
In both of the known methods, the components and the three-dimensional circuit arrangement are essentially produced at the same time, with the result that the method must be carried out by a chip manufacturer.
SUMMARY OF THE INVENTION
The present invention is based on the problem of providing a method for the production of a three-dimensional circuit arrangement in which the production of individual components can take place independently of the construction of the three-dimensional circuit arrangement.
This problem is solved according to the invention by a method for the production of a three-dimensional circuit arrangement, area, at least one first circuit structure, a first metallization plane and a first passivation layer which covers the first metallization plane, is connected to an auxiliary substrate via a first adhesion layer which is applied to the first main area, the first main area, area, at least one second circuit structure, a second metallization plane and a second passivation layer which covers the second metallization plane, is provided with a second adhes
REFERENCES:
patent: 4902637 (1990-02-01), Konduo et al.
Wolf et al, Silicon Processing For The VLSI Era, vol. 1, Process Technology, Lattice Press, pp. 182-195, 1986.
Ghandi, Sorab K., VLSI Fabrication Principles Silicon and Gallium Arsenide, John Wiley and Sons, Inc., pp. 587-613, 646-653, 1994.
T. Kunio et al., "Three Dimensional Ics, Having Four Stacked Active Device Layers", International Electron Devices meeting, Technical Digest, 1989, pp. 837-840. Month Unknown.
K. Oyama et al., "High Density Dual-Active-Device-Layer(Dual)-CMOS Structure With Vertical Tungsten Plug-In Wirings", International Electron Devices meeting, Technical Digest, 1990, pp. 59-62. Month Unknown.
Y. Hayashi et al., "Fabrication of Three-Dimensional IC Using Cumulatively Bonded IC (Cubic) Technology", 1990 Symposium on VLSI Technology pp. 95-96. Month Unknown.
Japanese Abstract, Semiconductor Device, S. Jiyunji, Publication number JP59155951, Publication date May 9, 1984, vol. 9, No. 8.
Japanese Abstract, M. Mitsuo, "Three-Dimensional Semiconductor Integrated Circuit", Publication Number JP63213943, Publication date Jun. 9, 1988, vol. 13, No. 2.
Bertagnolli Emmerich
Klose Helmut
Lebentritt Michael S.
Siemens Aktiengesellschaft
Tsai Jey
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