Cache coherent network adapter for scalable shared memory proces

Details Cache coherent network adapter for scalable shared memory proces Cache coherent network adapter for scalable shared memory proces

1997-07-10

2000-07-18

Nguyen, Hiep T.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711121, 711144, 711145, 711148, 711153, 711173, 709200, 709214, 709215, 709216, 709218, 709250, G06F 1208

Patent

active

060921552

ABSTRACT:
A shared memory parallel processing system interconnected by a multi-stage network combines new system configuration techniques with special-purpose hardware to provide remote memory accesses across the network, while controlling cache coherency efficiently across the network. The system configuration techniques include a systematic method for partitioning and controlling the memory in relation to local verses remote accesses and changeable verses unchangeable data. Most of the special-purpose hardware is implemented in the memory controller and network adapter, which implements three send FIFOs and three receive FIFOs at each node to segregate and handle efficiently invalidate functions, remote stores, and remote accesses requiring cache coherency. The segregation of these three functions into different send and receive FIFOs greatly facilitates the cache coherency function over the network. In addition, the network itself is tailored to provide the best efficiency for remote accesses.

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