Integrated circuit and method for forming and integrated circuit

Details Integrated circuit and method for forming and integrated circuit Integrated circuit and method for forming and integrated circuit

1996-01-18

1998-12-22

Bowers, Charles

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438672, H01L 2348, H01L 2144

Patent

active

058519238

ABSTRACT:
A method for forming an integrated circuit comprising providing a substrate comprising a node to which electrical connection is to be made; providing a layer of material outwardly of the node; and providing an electrically conductive plug through the layer of material and in electrical connection with the underlying node, the layer of material and conductive plug forming an interlocking discontinuity which effectively prevents displacement of the electrical conductive plug from the node. The present invention also contemplates an integrated circuit wherein an interlocking discontinuity comprises a projection which extends laterally outwardly relative to an electrically conductive plug, or a projection which extends laterally outwardly from a layer of material into an electrically conductive plug.

REFERENCES:
patent: 4728623 (1988-03-01), Lu et al.
patent: 4871689 (1989-10-01), Bergami et al.
patent: 4979010 (1990-12-01), Brighton
patent: 4997790 (1991-03-01), Woo et al.
patent: 5063175 (1991-11-01), Broadbent
patent: 5143861 (1992-09-01), Turner
patent: 5210054 (1993-05-01), Ikeda et al.
patent: 5219793 (1993-06-01), Copper et al.
patent: 5270254 (1993-12-01), Chen et al.
patent: 5286674 (1994-02-01), Roth et al.
patent: 5327011 (1994-07-01), Iwamatsu
patent: 5356836 (1994-10-01), Chen et al.
patent: 5368682 (1994-11-01), Park
patent: 5371410 (1994-12-01), Chen et al.
patent: 5408130 (1995-04-01), Woo et al.
patent: 5414221 (1995-05-01), Gardner
patent: 5464794 (1995-11-01), Lur et al.
patent: 5470790 (1995-11-01), Myers et al.
patent: 5583380 (1996-12-01), Larsen et al.
patent: 5612252 (1997-03-01), Lur et al.
patent: 5616960 (1997-04-01), Noda et al.
patent: 5710460 (1998-01-01), Leidy et al.
Anonymous, IBM Tech. Disc. Bulletin, 38(6)(1995)405 "Method of anchoring contact or via plugs by producing lateral recess in ILD or IMD films", Jun. 1995.
Anonymous, IBM Tech. Disc. Bulletin, 34(4B)(1991)288 "Rooted refractory metal on AI-Cu . . . ", Sep. 1991.
T. Hasegawa et al., Jpn. Soc. Appl. Phys.: Proc. of 52nd Fall Meeting, 1991, p. 718 "Via filling on Al . . . using al isotropic etching", 1991 no month.
IBM Technical Disclosure Bulletin; Bipolar Transistor Structure With Extended Metal Base Contacts and Diffused or Implanted Emitter vol. 22, No. 5 pp. 2123-2126 no month.
Anonymous, IBM Tech. Disc. Bulletin, 38(6)(1995)405 "Method of Anchoring contact or via plugs by producing lateral recess in ILD or IMD films" -Jun. 1995.
Anonymous, IBM Tech. Disc. Bulleton, 34(4B)(1991)288 "Rooted refractory metal on Al-Cu . . . "-Sep. 1991.
T. Hasegawa et al., Japan Society of Applied Physics, Proc. of 52nd Fall Meeting, 1991, p. 718 "Via filling on A1 . . . using A1 isotropic etching" 1991 no month.

Affiliated with

Also associated with

Rating

Integrated circuit and method for forming and integrated circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Integrated circuit and method for forming and integrated circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit and method for forming and integrated circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2047271