Apparatus and method for programmable delays using a boundary-sc

Details Apparatus and method for programmable delays using a boundary-sc Apparatus and method for programmable delays using a boundary-sc

1998-11-12

2000-07-18

Tokar, Michael

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

326 39, 326 16, 326 93, 714727, G06F 738, H03K 19173, G01R 3128

Patent

active

060912618

ABSTRACT:
The invention is a system that provides programmable clock delays for logic circuits. The system makes use of the boundary-scan register chain incorporated into logic devices for testing purposes. In the invention, delay code values are loaded through the boundary-scan register chain into delay code registers. The delay codes are then used to program the value of delay elements in the logic circuit. An evaluation logic circuit can be included to compare the output data with an expected test pattern and thereby verify the acceptability of the delay values. The invention thereby allows delays to be adjusted to correct functionality and/or optimize circuit performance without requiring modifications to the circuit design.

REFERENCES:
patent: 5740410 (1998-04-01), McDermott
patent: 5926053 (1999-07-01), McDermott et al.
patent: 5948114 (1999-09-01), Klingler
patent: 6020757 (2000-02-01), Jenkins, IV

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