Local interconnect patterning and contact formation

Details Local interconnect patterning and contact formation Local interconnect patterning and contact formation

1997-12-16

2000-07-18

Niebling, John F.

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438952, H01L 2144

Patent

active

060906944

ABSTRACT:
A method for forming a semiconductor device to produce a more distortion free via for interconnecting levels within a device or forming a connection between an external surface and an internal layer within a device includes the step of substituting a material similar to an etch stop adjacent one of the layers for the ARC. In other words, an etch stop is placed over the metal layer formed on a layer within the device. This is followed by a layer of silicon dioxide (SiO.sub.2) and then by a layer of material similar to the etch stop. Photoresist is placed on the layer of material similar to etch stop. The photoresist is exposed to light to form the location of the vias. The layer of material similar to etch stop, and the SiO.sub.2 layer are then removed in separate etching steps to form the via pathway from the resist to the etch stop adjacent the metal of the layer selected to be interconnected by the via. The resist can then be removed. This leaves the material similar to the etch stop located adjacent one surface of the SiO.sub.2 layer, and leaves the etch stop covering the metal in the via opening. One etch step can now be used to remove the etch stop covering the metal in the via opening and to remove the material similar to the etch stop located on the SiO.sub.2.

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