Method of making a latch up free, high voltage, CMOS bulk proces

Details Method of making a latch up free, high voltage, CMOS bulk proces Method of making a latch up free, high voltage, CMOS bulk proces

1988-11-25

1991-04-09

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 29, 437 44, 437 30, 148DIG53, H01L 21265

Patent

active

050064770

ABSTRACT:
A process for forming MOS devices having graded source and drain regions. The source and drain regions are lightly doped by ion implantation and then subjected to thermal cycling to diffuse the implanted impurities. The source and drain regions are then heavily doped to form source and drain regions having a heavily doped subregion and a lightly doped subregion. Devices made pursuant to the process, which can be made less than one-half micron, are not subject to gate oxide charging and have high snapback voltages.

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Lu et al.; "A Folded Extended Window MOSFET for ULSI Applications"; IEEE Electron Device Letters; vol. 9, No. 8, Aug. 1988; pp. 388-390.

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