Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1991-11-27
1993-09-14
Mintel, William
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257371, 257372, 257552, 257607, H01L 2976, H01L 2994, H01L 2900, H01L 29167
Patent
active
052452093
ABSTRACT:
The impurity concentration of an n.sup.+ buried layer 51a in the region for forming a p channel MOS transistor 23 is higher than the impurity concentration of an n.sup.+ buried layer 3a in the region for forming an npn bipolar transistor 21. N.sup.+ buried layers 3a and 51a are formed on a p type silicon substrate 1. An n.sup.- well region 10 is formed as a region for forming npn bipolar transistor 21 on n.sup.+ buried layer 3a. An n well region 12 is formed as a region for forming p channel MOS transistor 23 on n.sup.+ buried layer 51a. While the performance of npn bipolar transistor 21 is maintained, the performance of a CMOS transistor formed of an n channel MOS transistor 22 and p channel MOS transistor 23 is improved. In a Bi-CMOS semiconductor device, the performance of a bipolar transistor portion is maintained, while preventing the formation of a punch through and improving the latch up tolerance of a CMOS transistor portion.
REFERENCES:
patent: 4694562 (1987-09-01), Iwasaki et al.
Fahmy Wael
Mintel William
Mitsubishi Denki & Kabushiki Kaisha
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