Method for planarized isolation for CMOS devices

Details Method for planarized isolation for CMOS devices Method for planarized isolation for CMOS devices

1991-10-31

1993-09-14

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437228, 437 67, 437 68, 437 72, 148DIG50, H01L 2176

Patent

active

052448274

ABSTRACT:
A method for forming field oxide regions includes the formation of cavities in a semiconductor substrate. A layer of thermal oxide is then grown on the substrate. A layer of planarizing material is deposited over the device, filling the cavities. The planarizing layer is etched back to expose a portion of the cavities. A conformal layer of undoped oxide or a layer of polycrystalline silicon that is converted to oxide is deposited over the device, followed by a second layer of planarizing material, The planarizing material and conformal layer are then etched back to expose the active areas in the substrate.

REFERENCES:
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"Buried-Oxide Isolation with Etch-Stop (BOXES)" by Robert F. Kwasnick, et al, IEEE Electron Device Letters, vol. 9, No. 2, Feb. 1988, pp. 62-64.
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"Latchup-Free CMOS Structure Using Shallow Trench Isolation" by Y. Nitsu, et al, IEDM 85, pp. 509-512.
"A New Bird's-Beak Free Field Isolation Technology for VLSI Devices" by Kei Kurosawa et al, IEDM 81, pp. 384-387.
"A Simplified Box (Buried-Oxide) Isolation Technology for Megabit Dynamic Memories" by T. Shibata et al, IEDM 83, pp. 27-30.
"Trench Isolation Prospects for application in CMOS VLSI" by R. D. Rung, IEDM 84, pp. 574-577.

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