Semiconductor memory device

Static information storage and retrieval – Systems using particular element – Flip-flop

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365 72, G11C 1300

Patent

active

055047050

ABSTRACT:
A contact hole connecting the source region of a LDD construction driver transistor and a grounding wiring layer (Vss) is provided in self-alignment with respect to a gate electrode of a driver transistor. With the source region formed by impurity introduced through the contact hole, the driver transistor is provided with asymmetric source/drain structure. By this, the on current of the LDD construction driver transistor can be improved without increasing the transistor size. Furthermore, imbalance of diffusion layer resistance in the source region can be reduced to improve stability of cell operation.

REFERENCES:
patent: 4864374 (1989-09-01), Banerjee

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