Semiconductor memory device for making column decoder operable a

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

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365193, G11C 800

Patent

active

061282472

ABSTRACT:
A semiconductor memory device is disclosed, in which the output timing of an operation enabling signal for activating the column decoder can be suitably determined according to the RAS access time. The semiconductor memory device comprises a memory cell array; a row decoder for decoding row address data for designating a word line; a column decoder for decoding column address data for designating a data line; and a column decoder control section for outputting an operation enabling signal for making the column decoder operable to the column decoder. The column decoder control section determines the output timing of the operation enabling signal according to a determination of whether a sufficient RAS access time is obtained.

REFERENCES:
patent: 5642326 (1997-06-01), Sakurai et al.
patent: 5745429 (1998-04-01), Cowles et al.
patent: 5812492 (1998-09-01), Yamauchi et al.

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