I/O interface cell for use with optional pad

Details I/O interface cell for use with optional pad I/O interface cell for use with optional pad

1995-06-06

1996-04-02

Westin, Edward P.

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

326 41, 326101, H03K 19177

Patent

active

055044395

ABSTRACT:
In a programmable integrated circuit device, a pad interface structure is provided in which the number of pads connected to the interface structure is selectively changed without redesigning the interface structure or redesigning the chip interior.

REFERENCES:
patent: Re34363 (1993-08-01), Freeman
patent: 4124899 (1978-11-01), Birkner et al.
patent: 4706216 (1987-11-01), Carter
patent: 4750155 (1988-06-01), Hsieh
patent: 4758745 (1988-07-01), Elgamal et al.
patent: 4758746 (1988-07-01), Birkner et al.
patent: 4821233 (1989-04-01), Hsieh
patent: 4870302 (1989-09-01), Freeman
patent: 4937475 (1990-06-01), Rhodes et al.
patent: 5023606 (1991-06-01), Kaplinsky
patent: 5148390 (1992-09-01), Hsieh
patent: 5198705 (1993-03-01), Galbriath et al.
patent: 5243238 (1993-09-01), Kean
patent: 5258668 (1993-11-01), Cliff et al.
patent: 5260611 (1993-11-01), Cliff et al.
patent: 5260881 (1993-11-01), Agrawal et al.
patent: 5267187 (1993-11-01), Hsieh et al.
patent: 5280202 (1994-01-01), Chan et al.
patent: 5317210 (1994-05-01), Patel
patent: 5317698 (1994-05-01), Chan
patent: 5341044 (1994-08-01), Ahanin et al.
patent: 5349248 (1994-09-01), Parlour et al.
patent: 5424589 (1995-06-01), Dobbelaere et al.
patent: 5450021 (1995-09-01), Chiang
"The Programmable Logic Data Book", 1993, pp. 1-1 through 1-7;2-1 through 2-42;2-97 though 2-130; and 2-177 through 2-204, available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124.
"Xilinx Programmable Gate Array Book", 1989, pp. 6-30 through 6-44, available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124.
Morales, Luis, "Boundry Scan in XC4000 Devices", XAPP 017.001, Oct. 1992, pp. 1 through 19.
Weste et al., "CMOS VLSI Design, A Systems Perspective", 1985 by A, T&T Bell Laboratories, Inc., pp. 224-230.

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