Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Patent
1997-12-31
2000-08-15
Cabeca, John W.
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
711133, 711134, 711136, 711159, G06F 1200
Patent
active
061051152
ABSTRACT:
A NRU algorithm is used to track lines in each region of a memory array such that the corresponding NRU bits are reset on a region-by-region basis. That is, the NRU bits of one region are reset when all of the bits in that region indicate that their corresponding lines have recently been used. Similarly, the NRU bits of another region are reset when all of the bits in that region indicate that their corresponding lines have recently been used. Resetting the NRU bits in one region, however, does not affect the NRU bits in another region. A LRU algorithm is used to track the regions of the array such that each region has a single corresponding entry in a LRU table. That is, all the lines in a single region collectively correspond to a single LRU entry. A region is elevated to most recently used status in the LRU table once the NRU bits of the region are reset.
REFERENCES:
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patent: 5542066 (1996-07-01), Mattson et al.
patent: 5809280 (1998-09-01), Chard et al.
patent: 5809528 (1998-09-01), Miller et al.
patent: 5845309 (1998-12-01), Shirotori et al.
Mathews Gregory S.
Mulla Dean A.
Cabeca John W.
Intel Corporation
Kaplan David J.
Peugh Brian R.
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