Nonvolatile memory circuit device with low power consumption and

Details Nonvolatile memory circuit device with low power consumption and Nonvolatile memory circuit device with low power consumption and

1989-03-06

1991-03-19

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

365203, 365185, 365204, G11C 700, G11C 1134

Patent

active

050016687

ABSTRACT:
A column decoder is driven by an intermediate potential VDD from a circuit for generating an intermediate potential between a Vcc potential and a Vss potential, and a column selection output having a swing width of the intermediate potential is supplied to the gates of column selection transistors to limit a current flowing therethrough. In the data readout mode, a precharge potential generated from a dummy cell circuit acting as a reference potential generating circuit according to a precharging signal supplied thereto is compared with a logic level of "1" or "0" read out according to the memory content by means of a flip-flop acting as a sense amplifier, thus deriving a data readout output.

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patent: 4314362 (1982-02-01), Klaas et al.
patent: 4394748 (1983-07-01), Campbell, Jr.
patent: 4644501 (1987-02-01), Nagasawa
patent: 4769787 (1988-09-01), Furasawa et al.
patent: 4833646 (1989-05-01), Turner
patent: 4843594 (1989-06-01), Tanaka et al.
Yaron et al., "16KE.sup.2 PROM with New Array Architecture", Electronic Engineering, vol. 54, No. 666, p. 35-47.
Maruyama et al., "Wide Operating Voltage Range and Low Power Consumption EPROM Structure for Consumer Oriented ASIC Applications," IEEE 1988 Custom Integrated Circuits Conference (Apr. 11, 1988, pp. 4.1.1-4.1.4).

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