Boots – shoes – and leggings
Patent
1989-04-28
1991-03-19
Shaw, Dale M.
Boots, shoes, and leggings
G06F 752
Patent
active
050016628
ABSTRACT:
Methods and apparatus are provided for performing multi-gauge arithmetic operations in a microprocessor CPU. Special purpose instructions facilitate parallel processing of individual bytes or half words of data words without requiring that the processor's mode be separately controlled. A byte/half word mode flag is provided to control the "width" of narrow gauge operation. Add partial, substract partial and compare partial instructions operate on corresponding bytes or half words of two operands and return independent byte or half word results. Multiply partial instructions multiply byte or half word multiplicands by a common multiplier and return independent byte or half word products. The multi-gauge arithmetic operations of the present invention have particular application to graphics processing where repetitive operations are performed on large arrays of pixel data.
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Gooding et al., "Partial Byte Computations", IBM Technical Disclosure Bulletin, vol. 17, #7, pp. 1931-1932, Dec. 1974.
Chandra, "Matrix Multiplication on a Parallel Processing Machine", IBM Technical Disclosure Bulletin, vol. 19, #12 pp. 4830-4834, May 1977.
DeRose et al; "Near Optimal Speedup of Graphics Algorithms Using Multigauge Parallel Computers", Proc. of 1987 International Conf. on Parallel Processing, Aug. 17-21 1987, pp. 289-294.
Apple Computer Inc.
Shaw Dale M.
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