Semiconductor device with polycrystalline silicon emitter conduc

Details Semiconductor device with polycrystalline silicon emitter conduc Semiconductor device with polycrystalline silicon emitter conduc

1994-09-22

1995-11-28

Mintel, William

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257587, 257588, 257591, 257755, H01L 2972

Patent

active

054710855

ABSTRACT:
An n.sup.+ buried layer is formed on a surface of p.sup.- semiconductor substrate. An n.sup.- epitaxial growth layer and an n.sup.+ diffusion layer are formed on a surface of n.sup.+ buried layer. A p.sup.- base region and p.sup.+ external base region adjoining to each other are formed on a surface of n.sup.- epitaxial growth layer. An an n.sup.+ emitter region is formed at a surface of p.sup.- base region. An emitter electrode is formed adjacently to n.sup.+ emitter region. The emitter electrode is made of polycrystalline silicon doped with phosphorus at a concentration from 1.times.10.sup.20 cm.sup.-3 to 6.times.10.sup.20 cm.sup.-3.

REFERENCES:
patent: 4299024 (1981-11-01), Piotrowski
patent: 4927776 (1990-05-01), Soejima
patent: 5150184 (1992-09-01), Eklund
patent: 5258644 (1993-11-01), Tamba et al.
"Shallow Junction Materializes in Both of Bipolar an DPMOS. We Fix our Aim Achieveing 0.5 .mu.m", Hyakuse et al., Nikkei Micro Device, Feb., 1990, pp. 70-76.
"Bipolar Transistor Design for Low Process-Temperature 0.5 .mu.m BiCMOS", M. Norishima et al., IEDM 89, pp. 237-240, 1989.
"Dopant Redistribution in Dual Gate W-Polycidecmos and its Improvement by RTA", H. Hayashida et al., Digest of Technical Papers, VLSI Technology, pp. 29-30, 1989.

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