Programmable mode register for use in synchronized memory device

Details Programmable mode register for use in synchronized memory device Programmable mode register for use in synchronized memory device

1999-08-02

2000-08-15

Nelms, David

Static information storage and retrieval

Addressing

Sync/clocking

36523008, G11C 800

Patent

active

06104668&

ABSTRACT:
Disclosed is a nonvolatile semiconductor memory device which comprises a mode register for storing the data for controlling plural operating modes, for instance, the RAS and the CAS latency, the burst length, and the burst type, of the memory device. The mode register of the present invention comprises a plurality of programmable elements, and a default value of the mode register is set depending on whether or the programmable elements are programmed. Furthermore, each of the programmable elements is comprised of the same element as the memory cells of the memory device. With the present invention, various default values for the mode register are set in accordance with the user's requirement without an additional process step.

REFERENCES:
patent: 5771199 (1998-06-01), Lee
patent: 5808948 (1998-09-01), Kim et al.
patent: 5812475 (1998-09-01), Lee et al.
patent: 5854769 (1998-12-01), Lee
patent: 5986918 (1999-11-01), Lee

Affiliated with

Also associated with

Rating

Programmable mode register for use in synchronized memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programmable mode register for use in synchronized memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable mode register for use in synchronized memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2014665