Semiconductor memory device having a large band width and allowi

Details Semiconductor memory device having a large band width and allowi Semiconductor memory device having a large band width and allowi

1999-09-21

2000-08-15

Mai, Son

Static information storage and retrieval

Read/write circuit

Bad bit

36523002, G11C 700

Patent

active

061046485

ABSTRACT:
A memory cell array includes a normal memory cell array divided into a plurality of memory blocks, a row redundant circuit and a column redundant circuit. Independent data lines are provided for the normal memory cell array, the row redundant circuit and the column redundant circuit, respectively. A data line shift circuit selectively connects each data I/O line to a global data bus. A redundant control circuit generates a shift setting signal corresponding to the defective address for setting a connection form in a data line shift circuit when an address signal matches with a defective address.

REFERENCES:
patent: 5687125 (1997-11-01), Kikuchi
patent: 5892718 (1999-04-01), Yamada
patent: 5978290 (1999-11-01), Fujita

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