Receiver and transmitter-receiver

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

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Details

329307, 329325, 455255, 455260, H03D 324

Patent

active

056617658

ABSTRACT:
A receiver comprises a demodulator for demodulating a received signal, a clock recovery circuit for regenerating a clock phase-synchronized with a symbol clock component included in the received signal and a frequency offset compensating unit for controlling a variable division ratio of a variable divider constituting a phase-controlled loop of the clock recovery circuit so as to compensate for a frequency offset corresponding to a difference between a frequency of the symbol clock component included in the received signal and a free-running frequency of the clock recovery circuit. The receiver is constructed such that the compensation for the frequency offset is performed with operation timing different from that of the clock recovery circuit.

REFERENCES:
patent: 3702379 (1972-11-01), Peterson et al.
patent: 4847876 (1989-07-01), Baumbach et al.
patent: 4870684 (1989-09-01), Arai et al.
patent: 4926447 (1990-05-01), Corsetto et al.
patent: 4959844 (1990-09-01), Walp
patent: 5533059 (1996-07-01), Tsup

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