RAM-logic tile for field programmable gate arrays

Details RAM-logic tile for field programmable gate arrays RAM-logic tile for field programmable gate arrays

1994-10-19

1995-11-07

Hudspeth, David R.

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 44, 326113, H03R 19177

Patent

active

054650550

ABSTRACT:
An improved RAM-logic tile (RLT) for use in a field programmable gate array (FPGA) is presented. The RLTs are located at the intersection of global horizontal and vertical lines. Wiring segments run locally between RLTs and contain programmable antifuses for connecting segments within an RLT and to neighboring RLTs. The RLTs are implemented with transmission gates and can be efficiently configured into a memory structure and/or logic device.

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