Fault alignment control system and circuits

Details Fault alignment control system and circuits Fault alignment control system and circuits

1982-05-24

1984-12-18

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Bad bit

365230, 371 11, G11C 1140

Patent

active

044894031

ABSTRACT:
The makeup of memory words is controlled by a memory address permutator that permits up to 2.sup.n ! input bit combinations. The particular combinations used in any decoder is dependent on the particular application. The new permutator also permits scattering of certain faults throughout the usable memory address space while simultaneously accumulating other faults in deallocated sections of the memory.

REFERENCES:
patent: 3644902 (1972-02-01), Beawsoleil
patent: 3781826 (1973-12-01), Beawsoleil
patent: 3812336 (1974-05-01), Bossen et al.
patent: 3897626 (1975-08-01), Beawsoleil
IBM Technical Disclosure Bulletin, vol. 16, No. 4, Sep. 1973, p. 1245, Address Reconfiguration for Large-Scale Integrated Memory Yield Enhancement, D. C. Bossen et al.

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