Structure of SRAM cell and method for fabricating the same

Details Structure of SRAM cell and method for fabricating the same Structure of SRAM cell and method for fabricating the same

1998-03-17

2000-10-03

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257366, 257371, 257374, 257393, 257401, 438153, 438154, 438157, 438199, 438266, 438283, H01L 2972

Patent

active

061277045

ABSTRACT:
A CMOS SRAM cell includes a substrate divided by a well trench into an n well region and a p well region, first and second active regions each having a V shape, formed symmetrical relative to each other, and having the well trench in between, third and fourth active regions formed symmetrically relative to each other and offset from the second active region, first and second gate lines each crossing the first active region, the well trench, and the second active region, and a third gate line crossing the third and fourth active regions.

REFERENCES:
patent: 5179038 (1993-01-01), Kinney et al.
patent: 5332688 (1994-07-01), Hashimoto et al.
patent: 5534450 (1996-07-01), Kim
Akinori Sekiyama et al., A 1-V Operating 256-kb Full-CMOS SRAM, IEEE Journal of Solid-State Circuits, vol. 27, No. 5, May 1992, pp. 776-782.

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