Semiconductor memory device and a manufacturing method thereof

Details Semiconductor memory device and a manufacturing method thereof Semiconductor memory device and a manufacturing method thereof

1992-05-12

1994-05-24

LaRoche, Eugene R.

Static information storage and retrieval

Systems using particular element

Capacitors

365 51, 365182, 257301, 257302, G11C 1300

Patent

active

053155432

ABSTRACT:
A semiconductor memory device includes a single crystalline semiconductor substrate having a main surface, a plurality of active regions formed at the main surface, and an isolation region which is formed at the main surface and isolates the active regions from one another. Each of the active regions has a transistor region and a capacitor region. The capacitor region has a trench formed in the single crystalline semiconductor substrate. An inner wall of the trench is covered with an insulating layer. At least a portion of the transistor region and the insulating layer are both covered with a semiconductor layer. A portion of the semiconductor layer which covers at least the portion of the transistor region is an epitaxial layer. A portion of the semiconductor layer which covers the insulating layer is a polycrystalline layer, which functions as a storage node of a capacitor. A semiconductor memory device is manufactured by forming an isolation region for isolating a plurality of active regions from one another at a main surface of a single crystalline semiconductor substrate, forming a trench in at least a portion of the active regions of the single crystalline semiconductor substrate, covering an inner wall of the trench with an insulating layer, forming a polysilicon seed film on the insulating layer, and growing a single crystalline silicon layer and a polysilicon layer respectively on an exposed portion of the top surface of the single crystalline semiconductor substrate and on the polysilicon seed film simultaneously and selectively.

REFERENCES:
patent: 4803535 (1989-02-01), Taguchi
patent: 5047815 (1991-09-01), Yasuhira et al.
T. Kaga et al., IEDM 87, pp. 332-335, "A 4.2 .mu.m.sup.2 Half-Vcc, Sheath-Plate Cap. DRAM Cell Self-Aligned Buried Plate-Wiring", May 1987.

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