Memory redundancy circuit

Details Memory redundancy circuit Memory redundancy circuit

1995-02-27

1996-11-26

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Bad bit

365201, 365195, 365226, 371 211, G11C 700, G11C 2900

Patent

active

055792650

ABSTRACT:
The disclosure pertains to a memory redundancy circuit. A main memory may, if there should be defective zones (defective columns for example), be replaced by a redundancy memory. A defective address memory is initialized during the testing of the main memory. During normal operation relating to access to the main memory, each main memory address is compared with all the defective addresses to replace the zone of the main memory with a redundancy memory. During the testing of the main memory, it is generally necessary to initialize each address of the defective address memory. This causes time to be lost if the main memory is fault-free. The disclosure provides for an inhibition circuit that can be used to put the defective address memory out of service or to make its operation ineffective, and to do so permanently. Application to integrated circuit memories.

REFERENCES:
patent: 4744060 (1988-05-01), Okajima
patent: 4858192 (1989-08-01), Tatsumi et al.
patent: 5113371 (1992-05-01), Hamada
patent: 5347484 (1994-09-01), Kwong et al.
patent: 5381370 (1995-01-01), Lacey et al.
patent: 5438546 (1995-08-01), Ishac et al.

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